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OK so what did we expect? Actually I don't know! What I do know is that for the purposes of simulation here in EC world, the inverter has undergone a severe transformation with the possible result of converting what was a useful component into little more than a high school toy.
I believe that the inclusion of gate timing delay parameters may have been intended as some form of time-based-hysteresis and this may in some way have been an attempt at providing more functionality? It may be that this was an attempt to imitate real world components which have propagation delay characteristics? All of this may be valid. But is it useful?
Like others here in EC world, I have found that the gates no longer do what I expect or want.
A much better and much more useful simulation characteristic would be to have a Schmitt trigger on/off attribute, OR to leave the old version of the gates as they were and add new Schmitt gates?
The hysteresis is the "dead gap" between 33% and 66% of rail voltage.
The Hysteresis of a Schmitt Trigger is the gap between the low point where the gate changes state and the high point. This gap is typically 33% of rail voltage and because this gap is so wide, it is very difficult for noise to enter the gate and cause false triggering. This makes the gate ideal for noisy situations but it will not amplify low-level signals and therefore cannot be used where small signals are required to be amplified. This is can be a drawback of a Schmitt Trigger in certain circuits.
However, apart from cleaning up logic input signals, the properties of Schmitt trigger inputs allow a whole range of RC timing circuitry to be built very easily including delays, oscillators and almost everything that we normally use the 555 timer for!
Sorry I cant show you this, as there is no Schmitt trigger implementation yet......
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