zorgrian

modified 8 years ago

Flip flop SCHMITT TRIGGER needs sorting out -help seeked... V2

291

02:29:46

THIS CIRCUIT EVOLVED AS AN EC COMMUNITY EFFORT INTO THE SOLUTION BELOW

http://everycircuit.com/circuit/5839835645607936

Now added a FET at the front end to lower input current. Or stated another way to increase the input Z. 

It will probably do the job, but I'd like the shape of output wave to be square not this feeble approximation!

I need a schmitt trigger made from discrete components because the use of 1/6 of one 74HC14,is absurd!

However this is the best I have been able to come up with even tho the input impedance is quite low compared to the chip versions.

It might work but it suffers from mark space ration problems, low input impedance and it doesn't quite square things up very well..

Can anyone provide insight ?

Obviously I do expect the trolling buggering slag-off attitudes that come from a few nasty minded personnel here at EC but it would be nice to think that one might get a real answer.

Actually its the first time I've asked for help directly!!!!!

73

published 8 years ago

roops1967

8 years ago

Here's the raw component layout for the schmitt you're taking about. Now it's upto you to tweak the biasing an resistors etc....

roops1967

8 years ago

http://everycircuit.com/circuit/4896673175437312

lankplay

8 years ago

Hgjfg

zorgrian

8 years ago

Cheers, i have looked at this topology. Cannot get it to function past 1 MHz.

roops1967

8 years ago

This where someone more knowledgeable than me steps in...

BillyT

8 years ago

I've played with roops1967 pulse a bit and get a fairly good shape out of it ... http://everycircuit.com/circuit/4626495573327872

BillyT

8 years ago

I now Increase the frequency, I've stopped about 3M because the output wave shaping is starting to look a bit horrible, it would appear that the RC effect of the the transistor and the circuit resistors come into play about this time, I am going to have a play with some FET circuita and see how they fare. http://everycircuit.com/circuit/6141991426719744

BillyT

8 years ago

As I suspected, in EC, the FETs capacitive effect is similar to the transistor, thus even though the biasing voltages are higher, the RC effect is very much the same. http://everycircuit.com/circuit/4931553544372224

zorgrian

8 years ago

Yeah of course, it could all be EC artifacts. However, real components also have capacitance etc. My main need is to square up an ugly sign based wave thats coming from the LO of a regenerative receiver. The LO is also the detector, amplifier, bfo, discriminator and filter so it does contain a complex waveform. If i turn up the regen of course the LO amplitude drowns out the other signals. However this is not really a good way to go as when the regen is high the frequency is often not spot on where you were listening. The thing does work with a 74hc04 but as i said I'm looking for a way to do this wirh discrete components.

zorgrian

8 years ago

I believe the EC transistor capacitance is around 5 pF. This is deduction from circuit behavior

zorgrian

8 years ago

Still above 3 MHz, this 5 pF will have an effect

zorgrian

8 years ago

Roops1967 circuit works better at higher frequency if the emitter resistance is removed

zorgrian

8 years ago

http://everycircuit.com/circuit/5839835645607936

2ctiby

8 years ago

Don't know if this is any help http://everycircuit.com/circuit/5018299804155904

zorgrian

8 years ago

2ctiby thanks! Yeah that does work. However, i note that you have adjusted the FET parameters. This is OK, but what real FET might this correspond to? If its based on a real FET then please let me know which one?

zorgrian

8 years ago

Also your sign wave signal has been increased to 7 volts which would create havoc inside a regenerative receiver unless shielded from the rest of the circuitry.

zorgrian

8 years ago

Im wondering how i can get this back to 1 volt input? Is this the FET adjustment? The switching point?

zorgrian

8 years ago

Checkout this

zorgrian

8 years ago

http://everycircuit.com/circuit/5839835645607936

2ctiby

8 years ago

A 1v a.c. input may be possible, but bear in mind that the Nmos gate needs to open at a voltage which is higher than the VTO. Notice that I was able to set the VTO to a shop possible value where the 7v gate was well above that. The 7v gate was also well above the drain v, enough to perform an Ohmic region full switching. Using a 1v at the gate may possibly not achieve all of that in practice....but it can be played with on EC to get a better understanding of the events and wave shapes.... http://everycircuit.com/circuit/5514839094198272 For a Nmos on your bench, you would need to run a few tests to obtain the specific Kn and VTO for that individual mosfet, and then aim to get the Ohmic switching from that starting point, (which could be put in the EC Nmos settings). Alternatively, if you have a few Mosfets around with a known low VTO (Vth), then trial and error may be easier to see if you can get any joy.

roops1967

8 years ago

zorgrian about the last one you posted, i believe that's propagation delay you're seeing not hysteresis. Dual thresholds disappear at lower frequencies if it's delay. But got to stress I'm no expert :)

zorgrian

8 years ago

Yes, i agree it may be propagation delay. However, the function needed here is voltage detection, which triggers rapid rise in output once the input has passed a certain point. Ideally like a switch that will detect voltage on and off points and then use these points for rapidly ramping up and then down the output as fast as possible.

roops1967

8 years ago

I guess your next step is build it on a breadboard, real components most likely behave differently at higher frequencies. All the more reason to have schmitt at high frequencies to clean up the noise

zorgrian

8 years ago

Obviously, the function needs to provide the same point of threshold detection for rising and falling edges. Here its done by biasing the input at 1volt DC with a sign wave input that falls below zero volts, such that the top half of the sign in, produces a positive square as rapidly as possible. Then the negative part of the sign in produces a space or no voltage output for that part of the cycle. It was suggested that this could be done with an op amp set to do this. I don't deny that this wouldn't work and there are examples of this on EC. But, i dont want to use a high speed op amp either. I specifically want to use discrete components.

zorgrian

8 years ago

2ctby, i can say that here the threshold of the FET is only important insofar as the point when the FET starts to switch on (and off). Really the FET isn't responsible for hard ramping of voltage, as this is already taken care of by the two BJTs. So i get what you're saying but most of this can be ignored by just knowing how much DC bias to apply to the input AC signal?

zorgrian

8 years ago

I wouldn't build this on a breadboard. No! No this will introduce all manner or stray inductance and parasitic capacitance. The only way to prototype this kind of circuit is Manhattan style, dead bug style or similar. This means soldering components onto bare PCB material. I use lands punched out of old PCB. Actually its quite good as the circuit built on bare PCB ends up laid out exactly as its drawn (or very similar). The through hole component legs are the the wires here. Sometimes i use a strip of PCB material cut off just for a bus bar, like for the VCC rail.

zorgrian

8 years ago

Thanks for all the help guys. I really appreciate it. This is what's good about the EC community and its worth protecting! I still say that trolls should be removed by a bigger impedance to enter. I.e. dont let them in for free. Then i also maintain that a block user button is needed. This would make EC far more attractive. Passive blocking of hyper trolls just doesn't work in all cases.

zorgrian

8 years ago

The trolls should only be allowed access to the simulation engine and not to the community comments, i believe.

2ctiby

8 years ago

Yes, the Nmos is responsible for the switching (which keeps the inevitable propagation in check too, and sets the hysteresis?), but the Nmos settings also effect the shape of the ensuing wave....that's why my output wave was square....the square final wave is very dependent on the Mosfet settings here, as well as the flip flop section.... not just its 'passing through the VTO switching point' .... Passing through the VTO and switching on will not produce a good square shape unless the Nmos Transconductance is also suitable.

2ctiby

8 years ago

Turn the Nmos KP in my schematic fully anti-clockwise, then slowly turn it up...see how the blue square shape changes....the same thing happens if the Width or Length is altered.....those three parameters form the individual Mosfet's Kn ... ie Kn= 0.5KP(W/L) ... it is unchangeable for every individual Mosfet...that's why it is a good idea to find the Kn for any individual one....The other variables (such as the Vgs etc) then need adjusting accordingly. On EC however, we can play with any of those variables to see what happens. Reality on a soldered PCB may be different though because EC does not cater for stray inductance and parasitic capacitance.

zorgrian

8 years ago

Just in case anyone hasn't seen the community effort, one of the solutions i will be prototyping is given below.

zorgrian

8 years ago

http://everycircuit.com/circuit/5839835645607936

zorgrian

8 years ago

2ctiby, i am unsure if your circuit behavior is the same as the one i just reposted above. Insofar, as sensitivity to the FET parameters???

2ctiby

8 years ago

What I just said still applies there....turn your W, L, and KP fully anti-clockwise on your setup there... see how your square wave then falls to pieces.

zorgrian

8 years ago

So far as i can say, i do not remember seeing the same parameters shown on FET data sheets. That is the parameters on EC mostly dont appear in the manufacturer data sheet. I guess the stuff you see on their data sheets is mostly lumped characteristics that are the result of many of those parameters we can adjust in EC?

2ctiby

8 years ago

The reason why your circuit there is more resilient to minor alterations is possibly due to your fixed dc 1v input rather than the circuit being dependent on your incoming a.c. signal.

zorgrian

8 years ago

Well I can't call it my circuit as it was a community effort. I only started it off. However, yes i agree that the DC bias gets round some of the FET input problems (characteristics)

hurz

8 years ago

Its really a pitty to see how @2cent messed up this thread and let you @zorgian.trap. dont listen to much what @2cent swaggers about mosfets. Its not helpful for your target schmitt trigger.

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