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https://www.youtube.com/watch?v=kt8d3CYWGH4
NOR GATE | NAND GATE
A B | Q | A B | Q
0 0 | 1 | 0 0 | 1
0 1 | 0 | 0 1 | 1
1 0 | 0 | 1 0 | 1
1 1 | 0 | 1 1 | 0
---------------------------------------------------------
R Q | S Q
S Q' | R Q'
---------------------------------------------------------
NOR
S R | Q Q'
0 0 | MEMORY (AS before)
0 1 | 0 1
1 0 | 1 0
1 1 | NOT USED
------------------------------------
NAND
S R | Q Q'
0 0 | NOT USED
0 1 | 1 0
1 0 | 0 1
1 1 | MEMORY (AS before)
------------------------------------
Case 1 : S=0, R=1, Q=0 & Q'= 1
: S=0, R=0, Q=0 & Q'= 1 memory
Case 2 : S=1, R=0, Q=1 & Q'= 0
: S=0, R=0, Q=1 & Q'= 0 memory
Case 3 : S=1, R=1, Q=0 & Q'= 0 wrong
: S=0, R=0, Q=0 & Q'= 1 !!!!!!!!!
NOT USED in SR LATCH
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