Following Ben Eater's guide on building an 8-bit computer. The circuit is Using both Astable and Monostable 555 timers, to act as the CLK signal and Pulse Signal respectively.
The SR -Latch configuration at the bottom is meant to be Bistable and acts as a control line for the NAND Gate circuit to output either the Astable or Monostable outputs.
This is my first logic design on this website and any thoughts or improvements would be greatly appreciated.
Thank you.
