EveryCircuit - Single supply

sshsslfun

7 years ago

👌

hurz

7 years ago

http://everycircuit.com/circuit/5504531604701184

crake

7 years ago

Thanks sshsslfun.

crake

7 years ago

I like what you did there, hurz. What motivated you to get rid of the feedback cap and the AC coupling cap at the input?

hurz

7 years ago

Cuz you need an extra 10V supply anyway (not a strong one, but its needed)

crake

7 years ago

I see that the circuit you posted no longer presents peeking at ~10MHz. How did you calculate 50pF at the final gain stage?

crake

7 years ago

At a certain point once C (of interest) becomes a short that positive feedback could become a problem, that's why I ask. It seems counter intuitive.

hurz

7 years ago

Have you calculated the underlaying transistor settings? If not, it wont make sense to start math to have a methode todo then irl. Its a bc547a (guess not) Bode plot is your friend to put a frequency compensation at this transistor in VAS. At exactly this one and not external at the feedback network which is custom made. BTW, same is valid for the offset compensation, some OpAmp do have extra external resistors for aligement.

crake

7 years ago

A link to an outline of your thinking would be helpful, or the general concept would be equally helpful.

crake

7 years ago

Looking at your transistor settings I think we could keep this discussion within the realm of EC. So, the answer to my question about the mathematical approximation of C at the final gain stage could be dealt with within the realm of EC.

crake

7 years ago

Between your circuit and mine there have been a few changes. I like your design. It's interesting. But, the transistor settings are the same. Beta 100, all else concerning BJT's the same.

hurz

7 years ago

So whats your problem we can help you with?

crake

7 years ago

Not sure where the circuit went. Anyway, you had a 50pF cap from the base to the collector at the final gain stage. I was asking how you calculated 50pF for your EC simulation, as your transistor settings are identical to mine.

crake

7 years ago

The circuit is still there. I probably copied the url incorrectly.

hurz

7 years ago

This is a standard capacitance as i already said for a VAS to limit the overall bandwidth. Its connected as a miller capacitance and its impact depend highly from the used transistor and its Hfe. Its capacitance is virtually increase by the factor of transistor gain. You know what a bodeplot is and you can see its impact.

hurz

7 years ago

BTW, this stage is not called “gain stage“ its the VAS, voltage adaptation stage

crake

7 years ago

Cool, that answered my question. Thank you

hurz

7 years ago

Why have you calculated 470uF for a 1kOhm load. Thats good for frequencies down to 0.34Hz while your input capacitor filters below 100Hz doesn't look to consistent.

crake

7 years ago

I made it really big to avoid time constant interaction while i was messing with different load resistances. I forgot to change it before saving. Fixed it now.

hurz

7 years ago

You forgot that before saving. But now output is for 10Hz while input is for 100Hz and above. Still not aligned

crake

7 years ago

Because I want the low frequency -3dB to be dictated by the input capacitor.

hurz

7 years ago

But it doen't make sense to support 10Hz -3 at ouput if input already cuts below 100Hz -3dB

crake

7 years ago

The circuit is consistent with what I said above. I am open to a better solution though, of course. What do you propose? Set both to 100Hz and then have a low freq -3dB be ~150Hz?

hurz

7 years ago

Its still your dual supply amplifier.