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592azy2circuitdude
modified 1 year ago

REV2 8 Bit Hex to Dec - Bin to BCD

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03:22:54
With the increase in workspace, I decided to review my past circuits to see if I could improve the simulation experience. This is a hexadecimal to decimal and/or a binary to BCD (Binary Coded Decimal) converter using the Double-Dabble algorithm. As an example, it converts "3D" Hex (0011 1101 binary) to "61" Dec (0110 0001 BCD). See the first versions here: 4 bit: https://everycircuit.com/circuit/6548980953251840. 8 bit: https://everycircuit.com/circuit/6747473873469440. They work, but I want to try and improve them. My objectives are: 1) Remove D-Type flip-flops: They seemed to cause much of the slow loading and lag. I replaced them with counters/registers, which seemed to help a lot. 2) Increase speed: This circuit is about 3 times faster than the original (and that's still kinda slow). 3) Reduce component numbers: The binary serial stream circuit is more efficient. I also saved on the reset logic by using the RESET pin on the counters. Still, this circuit is not running as fast as I would like. Does anyone know why? The whole circuit boils down to just a very large Moore State Machine with 10 state variables (counter outputs). The boolean Next State Equations are created with the logic gates. Shouldn't this be very fast for a circuit engine to solve? Can anyone help me with my objectives?
published 1 year ago
jason9
1 year ago
I don’t really know how to make this faster. Unfortunately, EC has a somewhat complicated logic gate model that includes things like gate transition delay which complicates the sim a lot more than a simple binary on/off output like the counters use. The only ways I can think of to speed up the sim are to replace the gates with something faster like more counters or even discrete transistors.
592azy2circuitdude
1 year ago
First, thanks, Jason, for taking the time to look into this. I didn't realize the propagation delay and logic gate model would slow down the simulation so much. But I'm inclined to agree.
592azy2circuitdude
1 year ago
I tried to run some speed tests, and I think the number of nodes a circuit contains may be a larger factor in determining run speed. For instance, try removing the 7-segment displays and 7-segment decoders. The lag becomes almost gone!
jason9
1 year ago
Oh, that’s interesting. I didn’t expect that. Seems like those components are pretty laggy, presumably due to the number of nodes involved. In that case there may not be much that can be done.

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