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maxmax_66
modified 5 years ago

Turing Machine 2 State - 2 Symbol

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03:35:00
This is a free running 2 state - 2 symbol Turing machine. There are five main parts to this setup- 1) A bidirectional 5 bit serial-in-serial-out shift register located along top. 2) A counter 3) Combinational logic to determine the state of the machine. 4) A 2 to 4 decoder connected to a programable ROM as finite state machine for an instruction table, located bottom right 5) a set of clocks for writing symbols, reading symbols, shifting and state change. This Turing machine consists of “infinite tape” as represented by the shift register. The shift register is limited to 5 bits, but simply think of it as an infinite tape of discrete cells each initially all zeros extending infinitely both left and right. The read and write head is represented by the counter which both reads the present symbol in the head (one or zero) and then writes a one into the cell. The register is then shifted, in this case it initially shifts left, the new state of the machine is read. Again, a one is written into the next cell and the shift register then shifts right. As long as the head reads a one, the machine will remain in this state, shifting right, until a zero is encountered. Then the machine writes a one, changes state again, shifting left through the ones until another zero is detected. In this way, the “tape”moves back and forth under the “head” writing all zeros to ones.
published 5 years ago
jason9
5 years ago
Do you know if it’s turing-complete (assuming infinite memory, of course)? If not, what more does it need?
maxmax_66
5 years ago
Interesting question. In the most abstract sense and as you say, assuming an infinite register, it is Turing complete with respect to Turing’s definition. In reality, given the finiteness of all memory systems, a 2 stare 2 symbol machine like this would not be Turing complete. At the very least, a halt state for finite systems would be required.
maxmax_66
5 years ago
When I find the time, I’ll try a Busy Beaver implementation, which would require a ‘halt’ state and a larger register (at least one more bit), space permitting, that is.

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