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kmo
modified 10 years ago

modified PLL ckt with indicator

3
10
182
02:44:59
pll ckt to make phase difference zero bt two waves activate the input signal by closing switch,then watch how they get zero phase difference.I put an indicator ckt to show a light only if it is that the zero phase difference is occured.LED will not be lit if the input signals is off or the two waves are not the same phase.you can change the signal frequency by varying C at the signal oscillator.
published 10 years ago
kmo
10 years ago
nice ckt right
hurz
10 years ago
Replace the 1uF cap at pin 5 of 555 with a 1kOhm and its working more or less.
ferlop
10 years ago
I tried it and found out that it does not phase lock, either with the capacitor or the resistor.
ferlop
10 years ago
Increase the capacitance of the capacitor from the 5K resistor to ground to 2uf, and exchange the other 1uf capacitor from pin 5 for a 1k resistor, watch the output of the and gate as well as the other two waves and it phase locks right in.
hurz
10 years ago
@ferlop, Dont know what you have tested but replace the cap with a 1k resistor works still fine.
ferlop
10 years ago
@hurz, it didn't work with or without the change of cap for resistor the first time I tried, but it is working now, it gets frustrating some times when things don't work right in EC.
hurz
10 years ago
Probably you also tuned the cap up or down while sim was running, this cause a voltage change! Anyway...
hurz
10 years ago
@kmo, now with your latest midification the circuit is boring, cuz both oscillators are equal in freerunning frequency! It would be more fun as you started with different frequencies as startconditions.
kmo
10 years ago
@hurz,I think you have read my description,so you misunderstanding something,this is phase locking ckt . Caz I am not a genius or pro , i cannot explain very well .Thus all i get .thank u for your attention at my circuitry
hurz
10 years ago
Make the left oscillator cap 80.1nF and you will see its not working, cuz the control voltage is differential and will sooner or later drop to zero and cant follow the phase error. The cap has to be changed to a resistor to constantly correct the phaseerror. Just my 2cents of PLL design.

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