Set Dominant Clocked Reset SR Latch 1Bit

This logic circuit allows "instanious" Latch when set goes high, doesn't wait for a clock/enable, and can only be reset on the rising edge on the reset pin when set is low. It is essentially a NAND SR latch's Q output fed into the S of a second NAND output, The Reset is on the first SR latch is the inverse of the second SR latch. Both SR latches can be made Set dominant using NOT AND combination. Double not and input to the reset of the first SR latch can be be simplified to a NOR. A circuit like this can be used to when the output directly influences the input and can stop racing. For instance output is a MOSFET shutoff, when the current reading in is the input. Using only a set dominant SR latch would result in racing. Looking for simpler ways to achieve the same result, or even an IC that achieves this. Comments welcomed.

published 6 years ago