|
UPDATED Description!:
Ps. Don't be scared, i promise it's more simple than it looks.
I have answered further down more in detail how a real DRAM works.
This circuit should give you a good understanding of how dram works but if you want the in depth details read EVERYTHING, if not read User manual. Good luck.
User manual: ---------------
1. Ignore every SPST switch they are just there to make the circuit clean
2. Use the top left controls to select what row you want (It's supposed to be a 2 - 4 binary decoder).
3. Use the middle right controls to write to any cell in a selected row. use the bottom logic source(LS) to select if you want to write HIGH or LOW and then enable write to any cell you want with the 4x LS on the right.
4. The lonely logic source on the middle left is used when wanting to refresh the cells on a selected row. It uses the Op amp output to resend charge back to the column its connected to. If a row is not refreshed in time the cells loose their charge.
5. the 7 segment-display shows what value is saved on the selected row (read).
Basic detail info:----------
The capacitors either store 1 or 0. 1 if the charge is >2.5V or 0 if <2.5V. The Op amp compares the capacitor charge with a reference voltage of 2.5V, so if the capacitor charge is greater than 2.5V then the op amp amplifies the signal to a readable 5V or 0V if the voltage is lower than 2.5V. The signal is sent from the op amp to a 7 segment dispaly which takes in 4 values coming from each capacitor on each column together forming a binary value and outputting the equivalent decimal number.
Precharge/sense amplifier :---------
In real DRAM using open bitline architecture, one sense amplifier is shared between two neighboring half-arrays. Each half-array connects to one side of the sense amplifier through its bitline. Both bitlines are first precharged to half the supply voltage (VDD/2). When a row is activated, the memory cells in that row connect to their bitlines. For each sense amplifier, only one of its two bitlines experiences a small voltage change caused by its connected cell, while the other bitline stays near the precharged level at first. The sense amplifier detects this small difference and quickly amplifies it to a full logic 0 or 1. Because the sense amplifier sits between the two half-arrays, it can serve both sides, which saves chip area by allowing one sense amplifier and one precharge circuit to support two columns.
Here are some sources that helped me understand DRAM:
Op amp: --------------
https://youtu.be/kbVqTMy8HMg
DRAM: ------------
https://youtu.be/LyqyIKSYlxw
https://www.youtube.com/watch?v=-Df09el4yDU&list=PLTd6ceoshpreE_xQfQ-akUMU1sEtthFdB
https://www.abhik.ai/concepts/memory/how-ram-works
If you are new to everything here i recommend having a good understanding of how the OP amp works and understanding what all components here is and what they do.
WARNING: I am not a professional i simply spent too many hours over too many weeks and or months (i dont remember) researching this. ദ്ദി ༎ຶ‿༎ຶ )
If you have any questions comment and ill answer.
|
