3 inverters just-about working correctly at 10MHz.
"Buffer stage" below is the part which goes, from top to bottom, RQDQ. (Now I'm wondering how much electronics knowledge George Lucas had. :)
I first tried just the one stage of two transistors without the buffer stage, and no emitter resistor. Output looked better with the emitter resistor.
Then I found it needs the buffer stage to drive the next gate if inversion is desired. If not, taking output from the emitter seems to work, but I didn't speed-test it.
Oh yes, TTL's logic 1 level is only 4V.
The buffer stage seems to slow things down slightly, but certainly cleans up the output!
Average current is probably a little over 10mA. At this speed, this must have seemed very good indeed after RTL, especially considering a NAND gate is no more complex.
Circuit copied from here, but the diagram is repeated all over the web:
https://www.electrical4u.com/transistor-transistor-logic-or-ttl/
This page tries to go into detail about the 'steering' transistor, (the one with its base pulled high):
https://www.allaboutcircuits.com/textbook/digital/chpt-3/ttl-nand-and-gates/
