D-CE Flip Flop w 555 Timer

108

00:53:44

D-Flip Flop with Clock Enable (CE)

Top cluster of NAND gates is a 2-to-1 MUX.  It enables or disables the clock.  

CE is control on MUX.
D is the top leftmost input
when CE is 0, clock is disabled.
when CE is 1, clock is enabled

Q=D on rising edge of clock.

Clock (Clk) is the 555 timer

published 10 years ago

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