D-Flip Flop with Clock Enable (CE)
Top cluster of NAND gates is a 2-to-1 MUX. It enables or disables the clock.
CE is control on MUX.
D is the top leftmost input
when CE is 0, clock is disabled.
when CE is 1, clock is enabled
Q=D on rising edge of clock.
Clock (Clk) is the 555 timer
