This circut demonstrates how one can make an T-flip-flop using RS-latch. So, RS latch
changes its state when rising (or falling) edge of the input signal comes to an input
which is "opposite" to the current state of the latch. In order to make a circuit
changing its state by each rising (or falling) edge of the input sequentially one can complete the RS-latch with the simple logic switching either the R input or or S input of the RS-flip-flop to the single common input the logic signal comes to. It can be implemented by connecting RS to the pair of AND elements having two inputs connected together and another inputs connected crosswise to the outputs Q and inv(Q) of RS-latch. Logically it's all clear
here but such simpliest version of the circuit (containing only logic and RS flip-flop) won't always work properly (especially in EC since the delay adjustment affects simultaneously to all the components and
can't be set separately say for RS and AND). Indeed when the latch starts to change its state with the coming input rising edge (for instance it comes to S input) the logic being connected to the outputs Q,inv(Q) quickly commutes opposite latch input (R) to the common input where the signal
of high logic level exists still which forces the RS-flip-flop to switch to the reverse state and so on. This circumstance results that the circuit enters in some kind of oscillatory mode while switching and doesn't work as desired. So the auxillary R, C, VD components forms some proper "artificial" delay. The opened diodes perfoms a quick transition from high to low signal level for AND inputs but when the diode is closed the switching time from low to high level (at the mentioned inputs) is determined by parameters of RC-circuit. That's how it works. Note that the output state (red) changes by every rising edge of input (green) signal. In other words this circuit divides frequency of the input by 2.
