Synchronous clock divider by 5

183

01:28:36

In order to preserve 50% duty cycle, additional flip flop with or gate required. Question: by looking at the waves at the outputs of three main state machine flip flops we can see that we need to delay and perform OR operation at the output of 2nd flip flop if we want to preserve 50% duty cycle. Is there easier way to find out which output should be delayed and ORed without looking at the waves first?

published 5 years ago

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