How a uc generate PWM. Only 4 bits to show principle, an 8 or 12 bits is less readable and take to much time on EC to count.
upper counter load compare value when lower pass to 0, prevent from false trigger.
lower counter count on 4 bits, this is the main device.
to compare if 2 binary numbers are equal, do a NXOR between each bits of same weight and AND all the NXOR, if result is 1 number are equal, if result is 0 they are not.
to compare to 0, NOR all bits (in EC only 2 input gate are available, so I NORed bit 0-1 and 2-3 then I ANDed the NOR gate to have a 4 bit NOR gate), if NOR equal 1 then all bits are 0, if equal 0 the number is not equal to 0.
The Set-Reset logic is made with 1 AND gate, 1 OR gate and 1 NOT gate. output of NOT goes to an input of AND, output of OR goes to the other input of AND, output of AND goes to an input of OR. the input of NOT gate is the reset and the free input of OR is set. the output of AND is the logic out with reset as priority and the output of OR is the logic out with set as priority.
it takes 1 cycle before a set occur, the 4 logic generator are the compare number.
