What.. The.. FET

By voltage delta from gate to source

So why is the voltage delta from drain to source seem to be what controls the triangle/bar animation? If I change Vdrain to 50V the symbol shows a triangle (partially open?). Raise Vgate to 50.something V and its a bar (fully open?) again... Shouldn't it remain "fully open" as long as Vgate is (x) volts above Vsource, just as you replied?

Keep the drain voltage at around 1V and play with the gate from 0 to 10V and measure the current drain source.

Done and added in circuit. Still has me puzzled.. The symbol changes when gate is over or under drain and drain to source current is only at 20-30 mA even when bringing the gate far above 10 V. With a MOSFET I would expect several Ampere rather than a few mA as soon as the gate-source voltage is above 5 or 10 V (logic level FET or "normal" power FET with higher gate voltage threshold).

Well.. Maybe I should not expect several Ampere when Vds is just 1 V but with Vd = 1 V, Vg = 10 V and Vs = 0 V (ground) I only get an Ids of 5.66 mA out of the default N MOSFET. That equals an Rds(on) of 176 Ohms??? Doubling Vg didn't improve the current/resistance that much, still tens of Ohms of resistance. :-/

This is because EC default mosfets are very little once for integrated circuits ICs. Tune the width parameter hundred times up and its closer to a discreet one.

Thanks for that hint on which parameter to modify and how much. I had already started fiddling with width/length but have no idea what is considered "realistic". :-)

I don't think that altering the width or length in the mosfet will do much here on its own. I would try altering both pulse sources to have a zero minimum.....the left source max which feeds the gate can be made to fully open it at almost any v, but it is best to set it at 15 v for your circuit as a good starter. Now get rid of the pull down resistor...you no longer need it now that the zero min source is pulsing to zero. You can use a wide range of v on the rightmost source, but you need a resistor in series with that source in to the drain. When you have done all that, you can play at altering any of the above parameters carefully whilst ensuring that the gate is fully opening and fully closing the bar. Choose your required selection according to your requirements for drain current etc. Power dissipation can be quite high, but that is often the case with mosfets...hence the heat sink....the width, length can now be altered to help if you wish to move the goalposts instead of sticking to the 'off the shelf' EC defaults....I can put up a working model of these adjustments if the above is hard to follow.

EC is simulating a single fet in a cmos wafer. in reality a power hexfet is actually thousands of fets stacked together, so they behave differently. widen it up and bring the kp up.

http://everycircuit.com/circuit/5357032901705728

Mr 2cent in action. LOL