Prototype circuit that delays forwarding of digital signal.
The delay time is controlled via Rc(4.7K), C(10uF), and voltage divider resistors R1(39K) and R2(10K).
The SR flip-flop in its normal operation state keeps MOSFET in OFF state preventing C to charge. Wheen logic 0 is passed to the flip-flop SET pin, MOSFET is begining to charge C via Rc (T=C*Rc). The voltage divider acts a s a reference point for Op-amp. When Vc = Vdiv Op-amp applies logic 1 to NOT gate which then inverts the signal to RESET SR flip-flop and stop MOSFET from charging C.
