SR delay

149

00:52:28

Prototype circuit that delays forwarding of digital signal.
The delay  time is controlled via Rc(4.7K), C(10uF), and voltage divider resistors R1(39K) and R2(10K).
The SR flip-flop in its normal operation state keeps MOSFET in OFF state preventing C to charge. Wheen logic 0 is passed to the flip-flop SET pin,  MOSFET is begining to charge C via Rc (T=C*Rc). The voltage divider acts a s a reference point for Op-amp. When Vc = Vdiv Op-amp applies logic 1 to NOT gate which then inverts the signal to RESET SR flip-flop and stop MOSFET from charging C. 

published 7 years ago

hurz

7 years ago

okok, you say T=C*Rc, while Rc=4.7kOhm. In your circuit its 47kOhm and the MOSFET itself also adds some resistance. Taken the max startup current when the cap is discharged, its 52.9uA against 5V which is then 94.5kOhm in total and much bigger then you explained. So the mosfet adds another 47.5kOhm

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