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Digit levels:
0 1 2 3, 1V per level.
Truth table:
0 3
1 2
2 1
3 0
Much easier to design than a trinary inverter, but still not as good as binary. It's 1.5-2 times larger than 2 CMOS inverters.
I'm basically designing logic series from scratch to make these things, and finding I'm not very good at it (yet).
This is a primitive form of this gate design. The transistor thresholds should be adjusted for some overlap in turn-on regions.
I'm not too worried about the practicallity of multiple power supplies. Modern computers have voltage converters all over the place. Amusingly, this requires accurate MOSFET thresholds, the development of which enabled the elimination of multiple power rails for binary computers some decades ago.
It needed diodes so the level 1 and 2 FETs wouldn't drag on the 0 and 3 levels, respectively. Silicon diodes have too high a forward voltage, and I'm almost sure germanium integrated circuits are not a highly-developed technology,* so this uses MOSFETs with very low thresholds as diodes. There seems to be a problem with the diode for level 1: open the switch. It may not be a problem after threshold tuning.
*: MOGFETs, anyone? Metal-oxide-germanium... :)
The digit levels are weaker than intended.
It might be best to declare the weak voltages to be the proper levels and design accordingly.
On-chip size estimation by sum of transistor width:
* This circuit:12μm
* If diodes for 0 & 1 are P-channel: 16μm
* 2 CMOS inverters: 8μm
Bleh! lol
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