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djmoc
modified 10 years ago

successive approximation adc v3.0

2
3
224
03:26:23
push button to start 1 sample. 8 bits of sampling. had to remove sample and hold from previous versions because of spaces. v2.0 : http://everycircuit.com/circuit/4977061715247104 v1.0 : http://everycircuit.com/circuit/6226264596676608
published 10 years ago
Taz8du29
10 years ago
Wow ! Nice circuit ! But that's laggy ^^ I did something similar, but idk if it's faster, or slower ... http://everycircuit.com/circuit/5627591942733824
djmoc
10 years ago
didn't analysed all yours but at first it seems to be a linear that count not a successive approximation. don't know what you mean by faster slower but if you think about conversion time, mine take n + 1 clock to complete where n is bit number and with sample and hold it takes 1 more clock. I made this for real with an FPGA and it can take a clock of 400kHz with decent precision and no special care. I made it for fun, not for real use... there is plenty of cheap converter for less than 5 bucks that will be better than this one.
Taz8du29
10 years ago
Faster/slower is for the number of clock cycles ... Mine is fast approx because it firstly check with big steps, then with smaller ones. I did it for fun too !! I know that some ADCs (pretty cheap now) are using ~1024 op amps to achieve 1-clock resolution !!

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