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Here I try to create an alternating half bridge switch using two NMOS (the right most pair of FETS). The challenge was getting the highside FET to switch because its gate-source voltage would be dependent on the output pin (drain of lowside FET) which is a floating point (switching output). Therefore, the capacitor is added to act as a 'virtual constant voltage' supply for the driver of the highside FET, referenced to the switching output node.The capacitor is charged with the first few pulses, to which it charges enough voltage to be able to drive the highside FET. This bootstrapping concept is very similar to the basic clamping circuit.
The two logic sources in the middle of the circuit is only there to act as 'gates'/Enable for Highside/Lowside use.
For Improvements:
- The control circuit definitely needs improvements. I am having trouble on translating the control signal voltage for the highside reference. Currently, the control circuit is referenced to the ground, which means that the driving voltage for highside goes from approx 0V - 20V (wrt gnd), which is not what I intend, and different compared to 0V-5V for the LowSide. The Goal is to make the highside driving voltage vary from 0V-5V as well with respect to the switching output.
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