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They are weird. Trying to watch the current flow depending on 1 or 0 from the left most input. Treat top 1 as VDD and bottom 0 as GND. NMOS transistor is on top, PMOS transistor is on bottom.
Turns out, if control (input at gates) is 1, then the PMOS is ON and the NMOS is OFF, causing the transmission gate to act as a very high resistance, keeping the output at whatever level it was previously. But if the control is 0, then the PMOS is OFF and the NMOS is ON, causing the transmission gate to act like a wire, passing the input right along to the output.
Cool!
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