modified 10 years ago

D-CE Flip Flop Digital In

00:30:26

D-Flip Flop with Clock Enable (CE)

Top cluster of NAND gates is a 2-to-1 MUX.  It enables or disables the clock.  

If CE (clock enable) = 1, the clock can change Q, based on D (left, center-ish)'s 1 or 0 status.  If CD =0, the clock has no effect on Q, and neither does D.

Clock (Clk) is the lower digital in.

published 10 years ago

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