What it is: a bitwise 3 bit adder
What it does: sums three bits during one CPU clock half cycle - takes input from three data registers stored at the previous half cycle (unless the write/enable switches were and are off), and stores the output to the data register, set to be enabled with the write switch on at the next clock half cycle and sets the zero and carry flags if necessary. If the full adder of the most significant bit has a carry bit, the overflow flag is set.
What's inside: in order to achieve minimal transistor count, the most efficient way is to use two XOR gates and a hybrid dual AND-OR gate.
From the looks of this, it would take 34 transistors to build it, but free space is precious in ICs. Any way to get even more efficient in this circuit?
