CMOS Full Adder

435

04:37:59

What it is: a bitwise 3 bit adder
What it does: sums three bits during one CPU clock half cycle - takes input from three data registers stored at the previous half cycle (unless the write/enable switches were and are off), and stores the output to the data register, set to be enabled with the write switch on at the next clock half cycle and sets the zero and carry flags if necessary. If the full adder of the most significant bit has a carry bit, the overflow flag is set.
What's inside: in order to achieve minimal transistor count, the most efficient way is to use two XOR gates and a hybrid dual AND-OR gate.

From the looks of this, it would take 34 transistors to build it, but free space is precious in ICs. Any way to get even more efficient in this circuit?

published 8 years ago

szillver

8 years ago

2ctiby

8 years ago

You say that the most efficient way is to use 2 x XOR etc......How many Mosfets are needed for a single XOR?

Thrashard96

8 years ago

12 for a single XOR: two supplementary inverters (2 transistors each) and 8 for the (A'xB)+(B'xA) logic that outputs the XOR of A and B. It might not be THE most efficient way (sorry for phrasing it that way in the description), but I asked how to further reduce the transistor count.

2ctiby

8 years ago

I am wondering if a 7 set of Nmosfets can be of help....that could provide a XOR, then x2 = 14 Mosfets for your mentioned group. The extras after that should only be a few Mosfets, thus making a total of approx 20 in all ?

garr890354839

8 years ago

XOR= <A OR B> AND <A NAND B>; OR can simply be made from 2 diodes, AND is made from 2 inverters feeding into another inverter, NAND can be made by removing the final inverter in AND.

eekee

8 years ago

I made a half-adder without XOR at all. It's in gates, but maybe it'll help: http://everycircuit.com/circuit/5825132078825472

eekee

8 years ago

I'm curious about your hybrid dual AND-OR gate, but my brain's too small (or I'm too inexperienced :) to pick it out from all the rest.

Thrashard96

8 years ago

Using only nMOS would defeat the purpose of CMOS.

2ctiby

8 years ago

True, but then using Pmos with Nmos could be even better ie less than seven Mosfets http://everycircuit.com/circuit/6063098337427456 see Selmans response to my presentation

Thrashard96

8 years ago

That is interesting. The thing is, on the background, outside of EC, I'm working on an ALU topological design. We have an IC design course where we're taught the Euler's path, etc, and our course project is designing a specific ALU. I know the voltages and MOSFET properties differ in the software we use in university. The logic used in the schematic view, on the other hand, doesn't. Either way, thanks for giving a different idea compared to the conventional way of building circuits. I knew there had to be more ways of building the CMOS structures than Vdd-pMOS-nMOS-gnd design. I'll try incorporating these into my future designs.

Thrashard96

8 years ago

And eekee, the gate is described as: (AxB)+(CxD) using Euler's path.

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