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selman
modified 9 years ago

Experimental PLL

12
4
656
09:50:31
I recently started working with PIC micro controllers, on a project to make my own joystick. Since PIC18F2550 controllers support a USB protocol they were my first choice, but what fascinated me more than the PIC is that, USB 1.0 communication requires a clock rate of 48MHz which to my knowledge crystal oscillators cannot provide, instead the crystal oscillator output of 16MHz is scaled up to 48MHz, using a circuit called A phase locked loop. This circuit combines a VCO, frequency divider to have multiple frequency locks, a phase comparator using OpAmps (I hate EC's Logic gates) and a low pass filter. The VCO frequency is varied until the phase difference is nullified this is called a frequency lock, after this point the PLL maintains this frequency. One problem I'm having with this circuit is when the frequency of the VCO output (from the asynchronous counter) fed to the phase comparative is changed the frequency was supposed to change, don't know why. Any suggestions ???
published 9 years ago
hurz
9 years ago
Your reference oscillator is set on 50MHz. Suppose to be 16MHz, right? The divider is ÷16 but suppose to be ÷3, right? Otherwise the VCO must run at 16*50MHz which is much to high! The importante thing for a stable PLL is a well tuned overall loop gain. That means a known frequency change per volt of your VCO. The loop filter 1kOhm and 1nF is now at 159kHz and very very slow. Suppose to work also with 100pF and 1kOhm.
hurz
9 years ago
Check this, I just make a 4 times higher reference 16*4=64MHz http://everycircuit.com/circuit/5492062403428352
selman
9 years ago
Change the phase comparator input to VCO / 2, it stays at 64MHz
hurz
9 years ago
Yes sure, cuz a multiple interger in frequency is also in phase. A phase comparator just checks the phase and not the frequency. And your VCO is BTW much to wide in frequency range. For the. USB example a VCO 48MHz +- 1MHz would be much enough.

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