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Look at the circuit on the right ....
V=IR
With V=30v and R=185Ω
I=162mA current max ....it can't be more in that setup.
Now look at the circuit on the left .... with its gate bar half out indicating Saturation region.
V=30v (Vdd) and R=185Ω (Rd) just as before, but....
Id=81.0mA .... no more, no less ....it is fixed.
We have fixed Id to be (Id max/2) ....ready for our signal. The signal will be coming in at the gate.
Look at the left circuit gate volts Vgs ....
It is fixed at (rule of thumb) 1/3 Vdd ie Vgs=10v ....(bias divider resistors)
Look at the drain volts ....
It is fixed at Vdd/2 ie Vds=15v
We have set our required central point on the drain for both V and I .... that is our chosen Q point.
(There could be other choices, but not today .... and it is not similar to a bjt selection).
Any further small input signal at the gate will now have room to oscillate freely around the central fixed point.
Notice that Vds>(Vgs-Vth) and is fixed well-greater than the edge where Vds might slip in to Ohmic.
That is our first step in preparing for the Nmos amplifier ....fix the Q point well in to the Saturation region, where Id holds steady in a linear way even if Vds alters....only our Vgs signal will alter the Id when put in.
Look at the Nmos settings ....
(W/L)=2 so my choice of KP is also the Kn value.
I chose Kn=1mA/V² for easy maths but you could use any ...it effects the gain of the Nmos but we can impress with gain there another time if we wish!
I also chose an easy maths 1v for Vth. We can do that in EC because we are able to adjust Kn to ensure that we stay in Saturation etc... with a real Mosfet we would need to use fixed values as found for their Kn and Vth, then work around those with harder maths figures....but why bother in EC here for simulation demonstration only.
Keep the lambda setting at zero right from the start for now, for all EC saturation operations ! See footnote.
See how we can adjust the Nmos settings to suit our requirements once we know what we need in terms of Saturation, Q point and Kn ? ... I adjusted Rd till the Id was exactly the 81mA which I wanted at Q, but altering one of the bias resistors is an alternative option, as is altering the KP (eg try 185μA/V² with Rd 1kΩ)
We can either shift those values around by trial and error in EC here without any maths, until they look correct .... or we can use the maths, e.g. to find the Vgs given Id, Kn and Vth:
Vgs= √(Id/Kn) + Vth as a manipulation of Id=Kn(Vgs-Vth)²
Then Vgs= √(0.081/0.001) + 1
So Vgs= √81 + 1
∴ Vgs=10 as seen
Now we are all set to superimpose a small signal a.c. at the gate....then we can view our gain and Amplification by comparing our scope results with a maths model.
Earlier part 5 is here http://everycircuit.com/circuit/5707117962199040
Next part 7 here http://everycircuit.com/circuit/6525003752538112
Footnote:
NB:
The Saturation formulae in this example ignores channel length modulation (lambda) for clarity, but advanced users can adjust for it as reqd. eg: make lambda a reasonable 5m, then apply it in the full formula of
Id=Kn(Vgs-Vth)² (1 + [lambda x Vds]) ... see how that alters the Vds to 14mV and a revised Ids of 86.7mA as shown, confirming the formula.
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