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I had an idea of making a trinary inverter by "chopping a leg off" my quadritonic inverter, accepting that the output levels will not be the same as input levels. The offset can be compensated by a second inverter, or by supplying following op-amps with an offset reference voltage.
In my adder for example, the offset reference would be supplied to the non-inverting input (marked +) of the left-most op-amp. The adder is an example of something which should have buffered inputs.
Speaking of offsets, I don't see much point re-balancing this to make the logic levels match the signal polarity, as is done for example within the adder. The logic levels are:
Input of first gate & output of second:
+ 2V
0 1V
- 0V
Output of first gate, input of second:
+ 3V
0 2V
- 1V
2 inverting buffers are shown. Normally, one gate would be accompanied by a LTP or full op-amp, I think, but I wanted to make two complementary gates to see that the offset can go down as well as up.
For clarity, reference voltages are replicated to avoid having wires everywhere. Voltages are sorted by row across both gates.
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