This ADC uses the successive approximation DAC design. This design is more complex than a standard ramp counter ADC, but it's really faster.
You can get more infos here (well explained) : http://www.hardwaresecrets.com/how-analog-to-digital-converter-adc-works/
The voltage source on the left is Vref,
The right one is the input you want to compare.
The button on the bottom right corner is the counter and memory reset.
The output is in Hexa, and has to be read from bottom to top (LSB is the top redistor, MSB is the lowes resistor).
When the ADC reaches the correct value 2 solution are possible :
1) Vref = Vin, and counter stops
2) Vref is between 2 possible values and output will oscillate between the closest values (one higher & one lower)
If you know how to fix this (without lots of space) and reduce lags ... let me know :)
