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Bit of an experiment, this. I'm much more practiced with op-amps than making logic gates, so when I wanted to make a trinary adder an op-amp design came to me easily, mostly! I also thought that it might require less soldering, but now it's done I see there are an awful lot of resistors.
Balanced trinary digits are represented as '+' '0' and '-'. While it doesn't require anything like binary's "twos complement", it's got its own oddities. The columns are ones threes nines etc, but to write a two you need to use the threes column. It's a little like roman numerals in that way.
Input switches are on the left. Of each pair, the left switch selects + or - and the right chooses that selection or 0.
Red and blue LEDs show the state of the inputs and main output. Orange and light blue LEDs show the carry output.
Employs both op-amps and comparators. The comparators are distinguished in the schematic by 1 MV/V amplification. (The 1V/V amp in the top right is supposed to be a normal op-amp in unity-gain configuration, but the simulator chokes on that.) The comparators' output limits are +/-12V. (I'm working for power rails of +/-5V and +/-12V.) I wonder if the fast output swing of comparators might be a problem.
The main signal path is two op-amps in inverting configuration, unity gain, and mixing multiple inputs. This alone adds the inputs correctly in all cases except where both are + or -. When they are, the first op-amp's output is twice the normal + or - voltage and the wrong polarity. The two comparators detect this and compensate via the diodes and the second op-amp. The comparator outputs are also mixed to produce the carry output, which is buffered by the third op-amp (top-right).
Once I grasped balanced trinary arithmetic and of course op-amps, the only tricky part was getting the comparator outputs and diodes correct to fix the output. I love op-amps!
~ Lead Count
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For comparison with some future CMOS design, considering hand-assembling a computer. Not counting leds or their resistors, or input switches.
10.5 -- 3 op-amps, 3/4 of a 14-pin pkg
7 -- 2 comparators, 1/2 of a 14-pin pkg
20 -- 10 resistors in circuit
4 -- 2 diodes
6 -- 3 resistors for comparators
= 47.5 total
Addendum: I started to work out a CMOS design, but found it much more complicated. I was trying to work with binary at two different logic levels, and it was the kind of work which gives me a headache anyway. Op-amps were invented for analogue computers and there is a tremendous range of them. Balanced ternary being a digital system doesn't require high accuracy, so almost any op-amp will do, from a dozen transistors or (maybe) less to high-speed ICs.
Addendum #2: I forgot the carry input! It seems simple, just one more resistor, but I'll have to rework the carry compensation because the third input creates a second carry state.
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