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Just a way to better control rise-edge and fall-edge delay
Adjust the potentiometers to change the delay behavior. Top potentiometer is for rising-edge, and bottom one is for falling-edge.
Settings for the component idea:
※Logic High: same functionality as for the other digital components, including adjustment behavior
※Rise Delay: The time delay (in seconds between 1n and 100m) between the input becoming Logic “HIGH” and the output becoming Logic “HIGH”. Independent from the Rise Delay settings of other of these components
※Fall Delay: Ditto, but for Logic “LOW” and Fall Delay settings for other Propagation Delay components (PDCs)
For all PDCs, Rise and Fall delay cannot be more than 20 times that of the lowest of all of them (i.e. if the lowest value for either Rise or Fall, out of all the PDCs, is 1 ms, the highest value possible for both Rise AND Fall, for ALL the PDCs, is 20 ms)
and cannot be smaller than the gate delay
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