LED Matrix and Serial Memory

I’m wondering if you feel up to making a computer yet. You said in your profile that you managed to work out that a Fibonacci sequence generator is possible, and for simplicity, you could make a Turing-complete (can compute anything that you’re desktop computer can if given enough time) single instruction (URISC; Ultimate Reduced Instruction Set Computing) computer which has been demonstrated to be possible in real life. All of the demonstrations (except one where where usability wasn’t a factor) used TTA (Transport Triggered Architecture) which is where it moves data from memory slot to memory slot where if it tries to read from certain memory slots, and the contents of certain memory slots and possibly it’s neighbors go through an ALU with the function of the ALU depending on the memory slot, and most of the memory slots have no function and are for storage. I’m sure you could make a URISC with TTA and have two memory slots for addition (if you read from one you would either get it’s value or zero depending on the design and if you read from the other you will get the sum of the two) which can be used for memory (only one of the slots needs to be read from in my design for the Fibonacci program) and five more memory slots for the program and program counter for a total of 7 memory slots, with one more memory slot for memory and that’s constantly displayed on a seven segment display. With the memory slots being used for program and data simultaneously it would have to be considered von Neumann architecture rather than Harvard, but you could make it Harvard architecture instead with the program as either read-only or hardwired so that you can spend one clock cycle per instruction instead of one for a read and one for a write. If you want to know more about the design see the homepage for the WireWorld computer which is where a based most of this information from. I think in the computer the memory slot for the display was write-only, but if you’re trying to keep it minimal so it can fit in EC then you probably want to make it work as general storage while being constantly displayed. You will also need memory slots 6 bits big with 3 bits for source memory slot and 3 bits for destination memory slot, which is rather unfortunate as it doesn’t fit in the 4 bit memory of the EC counter. I hope you can work something out. This is the simplest design I can think of for a Fibonacci generator in EC. I might even give it a try myself.

If the memory slots are like this: 0=program counter, 1=memory and display, 2=program, 3=program, 4=program, 5=program, 6=program, 7=memory and addend, 8=other addend if written to and sum if read from. Then the program would go like this: 2=copy 7 to 8, 3=copy 1 to 7, 4=copy 8 (sum) to 1, 5=copy 6 to 0, 6=the constant 2. Now that I look at it like this it seems there are nine slots which would mean that each slot would need 8 bits (4 bits for source memory slot and 4 bits for destination memory slot), so maybe you should go for the Harvard architecture with the program (and program counter) as read only or possibly hardwired and the rest would be read-write. If you go for that method then memory slots 0 and 6 would not be considered part of the read-only program as both are either read from as part of an instruction (but not an instruction itself) or written to. That way you could use larger memory for the non-instruction slots to display bigger Fibonacci numbers if there is room for more memory.

What do you think of the idea? Later today I’ll consider trying to make it myself.

@jason9: TTA looks like a fancy name for serial memory like this circuit uses. :) Not really; as you say, TTA is more than just that. I'd recommend going with a serial architecture though, if only because it means you only need a 1-bit adder. I can't imagine a practical TTA design, but it's fair to say I can't imagine a lot of things unless I try very very hard. :) Hmm... I would seriously not recommend Harvard architecture because it means you need to pack in even more memory, somehow.

By the way, I thought 28 bits total memory was a reasonable upper limit for an EC computer. It's one full row, with 7 counters, taking 3/8 of the total space. I guess you might get two rows in if you're particularly brilliant at minimizing the rest of the logic. I was going to have 2 extra counters as 4-bit latches as well as those 28 bits.

Huh... TTA could entirely replace instruction decoding, which would save a lot of space. ... I think. I might be getting ideas, but I don't want to spend too much time on it.

If I ever said a Fibbonacci program was possible, I was mistaken. I was trying to fit it into 28 bits with 4 bit word size. On looking at the program carefully, I found I'd made a mistake and the corrected program wouldn't fit.

Actually, partially replace it. Would still need to decode a small destination address, at minimum.

About you not being able to imagine a practical design, the WireWorld computer uses URISC TTA and can compute the primes in a reasonable number of clock cycles (probably doesn’t use the best algorithm, but one better algorithm I can think of would use more and more memory as the number of primes found rises and that wouldn’t work with the computer only having 64 registers most of which are already used for either program or computing. Also, I read about at least one design of micro-controller that seemed pretty good, but that might just be because the makers of the website were good salesmen.

About you’re saying it was possible to make a Fibonacci sequence maker and you saying that that is not true, you said in your profile that you “found it hard to squeeze even a fibonacci sequence generator into those 28 bits” implying that it was hard but doable. Maybe I’m wrong about what you meant about that, but the first impression I got from that was that you were implying that it was still doable if hard.

Also, what do you mean by serial computer? Do you mean something equivalent to a Turing machine or Wang’s W machine?

You know, some operations would take a lot more room in TTA than in a regular architecture. Subtraction is basically free.

Okay, don't worry about my implications too much. I find words. I put them together. It's a crude process. :) I don't recall much about Turing's machine, or anything about Wang's. I mean a computer which processes 1 bit at a time. I actually envisioned it being serial just to save space, but treating the bits as groups of 4. It's probably not as good as the 1-bit computers which I heard mention of a long time ago. They were supposedly able to add numbers of any length, but I can't see how. I could probably work it out if I tried, maybe see what a state machine could do, but I've got other projects. I want to get on with my text editor (which is just a part of a much larger project), and I have a virtual modelling project on the go too.

How would certain operations take so much room on a TTA than on a regular computer? If on a regular computer the operations are simple because it already has a unit to do it than couldn’t a TTA computer also have a unit like that?

By the way, I made a Fibonacci generator, but I didn’t make an entire computer to compute it because every time I tried to build one EC kept crashing half way through building it.

I was wrong. I assumed a TTA design would need to store data to be added or subtracted in different registers, but it just needs to send the data into the ALU, doesn't it? In the case of subtraction, data and carry in need to be inverted. I could see how it would be done with XOR gates in a regular design, a bit from the instruction decoder governing whether the XOR gates invert or not. In a TTA design, that bit would come from the address lines, wouldn't it?

Cool you designed a Fibbonacci generator. About EC crashing when building dense circuits, I can usually get through it by saving very frequently, and just moving the next component a bit differently after each crash. That comes naturally to me, anyway. IIRC, sometimes it helps to move another component. Another thing that may help is moving the canvas so that the new component appears in a different place.

The way TTA works is that it stores data in special registers that if read from the data goes through an ALU before being read, but the information on the registers is preserved. So, if registers 6 and 7 were “add” registers then 6 would be a normal register and if 7 is read from then it will read the sum of 6 and 7 but 6 and 7 will still have their original information in them. So that way, different registers can “perform” different actions when read from but preserve the data inside them at the same. About EC crashing and building it differently each time helping with it not crashing, when I was building a computer I couldn’t remember where each component went each time I tried and I hadn’t even got the basic design down by then so that helped with keeping each try different, but it still crashed anyway and for some reason I hadn’t really felt like saving it half way through.

Sounds like the build was a headache! Also, if you don't mind me saying, it sounds like you're pushing yourself too hard or something, what with not feeling like doing something that makes sense. A lot of programmers get that way too. -- I don't see why TTA couldn't be write based as well as read based. :)

What do you mean by “write based” vs “read based”?

You're saying the operation depends what location is read from. I was thinking of a design which depends on which location is written to.

Ah, I see. That wouldn’t work so well with something like having an add function between two registers or “return one if both registers are equal else return zero” since those require two registers.

Add only requires memory and one register. The one register serves as both one of the operands and the result, usually. Related: It used to be common for one register to receive all results from the ALU, and be one of the operands too. That register was called the accumulator. -- You don't usually get a full 'return with value' at machine code level. An equality test is usually done by subtraction, then jumping based on flags set by the subtraction. Usually it's an alternate op-code, a modified subtraction which discards the result and just keeps the flags. XOR could work too, but doesn't give you the option of testing for less than or greater than. The flags for this are Z - all bits zero, and N - a copy of the highest bit which also indicates if the result is negative.

I see. Any ideas for implementing the computer in EC? I’d like to discuss the design with you for maximum compactness so as to fit in the schematic. I’m thinking to possibly use the counter IC’s load function as a large and gate for multiplexing/demultiplexing. What do you think? Also, if I’m going to upgrade my already existing Fibonacci generator to 8 bit, how do you think I should go about making the binary to BCD convertor? I know how to make one using 5 “add 3 if greater than 4” units, but that will be a bit big and might not fit.

Actually, it’s 7 “add 3 if greater than 4” units, not 5.

I tried again with the computer and I’m not sure it’s going to work with a normal design. Maybe we can try again with that serial computer idea of yours. How does a serial computer work? We could also see if we can implement Wang’s W machine to get it to work. I’m not really sure how to do that either though.

Ooh, how do you a counter IC as an AND gate? I look forward to seeing that, actually. :) I've never really 'done' BCD. My serial computer is mostly done, but there's very little room for instruction decoding: http://everycircuit.com/circuit/4523786908205056

What you do to use a counter IC as an AND gate for a multiplexer is the multiplexer decides which input to output and then the load input of the counter that’s connected to that input is activated and the reset input for the other counters is activated and then the counter let the signal pass like an AND gate with one input on and the other counters blocked the signal like an AND gate with one input off. I’ll look at your computer now.

I think the computer is coming along nicely. I’ve bookmarked it for easy access so that we can continue the discussion there where it is more relevant to the circuit were talking about.

Oh I see. That would save space, compared to AND gates. -- Thanks. :)