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Self explanatory Adc :) Slow it down to see the conversion in detail on the scope
Rework of :
http://everycircuit.com/circuit/6155885612367872
I weren't happy using all those logic trains in the original, wanted to use a single clock source (albeit many interleaved clocks here on EC), it ended up using extra logic to do so. But atleast it's coming closer to what can be made on a breadboard. Now just gotta think of a easy way to implement the anologue source that steps through the fixed voltages
Each character is represented by a voltage, it is presented to the adc in turn by the clocked voltage sources in series bottom right
The voltage of a character can be calculated by adding up the values of the corresponding segments shown below, multiply it by 0.0625, then add 0.03125 for tolerance. Obviously need to round it off
4
64 32
2
16 8
1
The clock(s) drives the 4 blocks of shift registers above it. It shifts 1 bit looped round 15 outputs, it does this by the NOT gate from the last output 15 triggering 1 count-up on the first block on startup. The first pulse out resets the 7 adc latchs. Next pair outputs 'set' the msb latch and then 'reset' if voltage is over threshold, and continues on through to the lsb latch. The NOT gate also clocks the 'load' of the 2 register blocks for the left 7segment aswell as restarting the loop again. All this happens in step with the clocked voltage sources
The outputs of the latchs go into 2 dacs and the right 7segment. The upper dac (least significant) has its lsb earthed, so the next seven are driven by the latchs. The dacs analog output gets 4 volts added and subtracts the clocked voltage sources. This output goes into the 16th register on the 4th block, the register's switch hi/lo threshold is 4 volts (half its 8 volts logic high). The logic hi will reset the corresponding adc latch when there's over voltage,. With this method I don't need to use a bulky comparator opamp or 'voltage controlled voltage source', clever huh? :P .... but probably won't work in the real world due to hysteresis
I hope the above was understandable... probably with my explanation it was clear as mud. It doesn't help either that the logic layout bottom left has gotten really messy in attempt to make everything fit, makes it very hard to follow! Let me know if need anything elaborated
Incase of you can't make out what the circuit is spelling out... 'Successive Approximation'... kinda obvious ;)
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