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Two stable states. And once it reaches one, it stays there.
State 1: Top output = 1 (logic 1 it corresponds to 5V at Voltmeter). Bottom output = 0. Close left switch. Right open, wait second or two.
State 2: Top output = 0 . Bottom output = (logic 1 it corresponds to 5V at Voltmeter).
Close right switch. Left Open, wait second or two.
Both switches closed: both outputs are 0 after some time. Inverts states and switches.
Both open maintains previous state, but logic 0 is not exactly 0 v, it is some microvolt.
At the beginning when both switched are open there is no power supply (no VDD, no GND reference). That it’s not possible for the circuit to “sit at 2.5 V” in real life, because: an inverter needs VDD/GND to define what “high” and “low” even mean.
Without supply rails, the outputs are effectively floating (undefined) .
What you’re actually seeing: the latch before it resolves (metastable / floating start) and you see it because this is a simulator.
Because the circuit is perfectly symmetric, it can temporarily sit at VDD/2 = 2.5 V (if VDD=5 V exists)
This is called a metastable point. Any tiny imbalance will break symmetry: transistor mismatch, noise, leakage, numerical rounding in the simulator.
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