BCD counter

249

04:34:11

Lower display is MSB while upper display is LSB. While LSB overflows it takes some time to increment MSB and reset LSB. Is there any other way to do it without any noticeable lag?

published 8 years ago

BillyT

8 years ago

Bit of a catch 22 there, the variables that you can change are 1. Sweep time, 2. Logic Train period & delay, and finally 3 And gate delay. Each one you adjust can affect another and the country rate you just have to play with them until you are happy with the result.

hurz

8 years ago

In reality you will not notice this, cuz this will happen within nano seconds. But if you need this e.g. for futher processing of numerical values, you can add an extra stage of latches which are loaded with the falling edge of your clock signal. Asyncron counter with syncron output. Hope this helps

hurz

8 years ago

http://everycircuit.com/circuit/5029751504240640

psydelysid

8 years ago

Good

BillyT

8 years ago

Nice fix hurz, everything gets synchronized.

hurz

8 years ago

Thanx, thats a standard methode to sync for e.g ripple carry adder/counter or any other async results having hazzards. In case of a counter, its better to use directly a parralel architectur.

harialingal

8 years ago

nice circuit @hurz

hurz

8 years ago

Thanks @harialingal!

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