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Well this tune is gonna get stuck in your head now :P
I was gonna right some inspirational quote, but couldn't fit the circuit. Plus it won't be inspirational for too long if its in a constant loop.. heh heh
Workings:
The voltage levels in the 'voltage train' at the bottom represents the letters. The 7bit adc is connected to the right 7seg display, the shift registers scroll em along. The period width delay dictates when then letters are presented to the adc for display. The spaces are gaps within delays of the letters
With 2.5% width giving 40 shifts within 800ms (slowed down) there are 17 voltage sources, but there are 26 letters in 'harder better faster stronger' ... I reduced 8 letters to 2, the 'er' gets repeated 4 times at regular intervals so they appear every 200ms at 10% width at the end of the voltage-train, the 'tt' in 'better' reduced to 1 with 5% width... and 1 more 'complicated' optimization
And all this needs to fit nicely into the timing of the adc and shift timings, 80ms divided by 4 so 20ms per shift. That 20ms times the 40shifts gives the 800ms period of the train. Sim speed is running at 240ms/s, EC's maximum allowed with all these timings.
Hope this makes sense, any questions fire away :)
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