modified 10 years ago

Why doesnt this work on EveryCitcuit

00:59:29

It gives an error

published 10 years ago

abobaker

10 years ago

You're connecting Q' to the data input .. But this flip flop configuration changes the output to match the input as long as the clock is high (e.g. output can change multiple times in only one clock cycle), so when you start simulation with the clock high it will oscillate and since EC has an ideal model for all logic gates so it'll oscillate at infinite frequency and the program does not converge giving you an error

indianachones

10 years ago

Both top gates are connected by their inputs. Cut that conection. And the not gate needs a logic input too

dylanmissuwe

10 years ago

Thanks abobaker

abobaker

10 years ago

Never mind .. urw

abobaker

10 years ago

Just of curiosity though, what were you trying to build ??

dylanmissuwe

10 years ago

Single input flipflop

abobaker

10 years ago

Well, you have to add another SR stage to prevent what's happening here .. Check this one out http://everycircuit.com/circuit/4841375538348032

dylanmissuwe

10 years ago

Thanks

erikjohanson2003

9 years ago

You have an odd number of inverting gates connected in a loop.

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