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EmilWojak
modified 5 years ago

Serial divisor by 5

2
1
217
02:12:50
Divides serially given binary number by 5. INPUT: Top left - serial input for the dividend value (green) Bottom left - CLK (blue) Above CLK - negated reset (set to zero to clear the internal state and wait 4 clock cycles to clear the output shift register) OUTPUT: Top right - input number (least significant hex digit) Middle right - input number dived by 5 (least significant hex digit) Bottom right - division remainder (0-4) DETAILS: The 4 D-flipflops at the top - input shift register The 4 D-flipflops below the top - output shift register The 3 D-flipflops at the bottom - internal state holding the value of the division remainder
published 5 years ago
RickTipps
5 years ago
how do you get those end of tracy nodes ? that will conect another position in the circuit ?

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