SRAM try 4

156

01:14:07

3 bits, 1 address.

Input is bottom left. Leftmost 3 switches are the bits to write. Set them as you like, then toggle Write Select, which is the 4th switch. A ground symbol separates input from Write Select.

Output requires Read Select be high. It's the switch at the top. As there is only one address and no common data bus, it's ok to leave Read Select high all the time.

Change Log:
2017-08-27
* Added output LEDs. Demi-bug: they light up when Read Select is low.
* Documentation
* Tidying up

published 8 years ago

eekee

8 years ago

I could have saved a gate per cell by using 4 NAND gates, but this way is nice and clear.

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