N MOSFET works on gate left open due to parasitic NPN transistors

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02:29:32

  How are both cases possible? When the Source  terminal and the Substrate terminal are connected together In MOSFET 

published 9 years ago

hurz

9 years ago

Don't think to complicated, EC models are not deep semiconductor P or N substrates. The gate voltage comes from 5pF drain-gate and gate-source capacitors which are charged equaly at DC operating point calculation at startup of simulation. If you remove the LED then you can see the gate is at supply half voltage. And because its infinite isolation of gate-source and gate to drain it keep the voltage forever. Hope this helps.

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