D flip-flop counter

213

02:59:51

This seems to work but at times runs all over the place and the frequency is unstable.

Help 😣

published 8 years ago

oOoZEUSoOo

8 years ago

I think this is the delay propagation of the JK flip flop ^^ Try with 10us it's better.

chx101

8 years ago

@oOoZEUSoOo I changed it to D flip-flop. I thought I was creating a new one. But I'm still having same problems plus timing inconsistencies

oOoZEUSoOo

8 years ago

Hi. You should have a look to the 74ls90 counter datasheets ^^

oOoZEUSoOo

8 years ago

It use JK flip flop but the last stage is an RS flip flop to erase bounce.

chx101

8 years ago

Ok thanks. I'll take a look at that

oOoZEUSoOo

8 years ago

But I've made a mistake ^^ There is different implementation.

oOoZEUSoOo

8 years ago

At last. I've just read delay propagation must be 100ns to be efficient. Try it but think to change your pulse periods to accelerate time.

roops1967

8 years ago

It's working fine. This behaviour is what you expect with asynchronous counter , looks cool ;)

roops1967

8 years ago

Actually you may be seeing convergence issues , this is when the sim is lagging due to calculations. Edit the values on your 7segment display to 5v minimise current resistance to 1ma 1m ohm, this will minimise the lag

roops1967

8 years ago

And while your at it change gate delay to 5.05ms and clock period to 334ms and simulation speed to 1s/s... trust me ;)

boooooooom

8 years ago

Why 5.05 ms roops? Ive been doing it since you helped me on a circuit 😉

roops1967

8 years ago

It's what the simulator allows to get 1s/s time, try reducing the gate delay an you'll see what I mean

boooooooom

8 years ago

Ah sweet! Thanks man @roops1967

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