modified 8 years ago

NAND gate SR flip-flop

01:07:57

This circuit is latched into SET state by default with 1 on the SET line and 0 on the RESET line. Flipping RESET back and forth at this state should prevent changes. Then, if you put both onto 1 and put SET to 0, it will swap positions, then RESET will be latched and you can toggle the SET line without change. If both are at 0, this is an invalid state and the behavior is 'undefined'.

published 8 years ago

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