Trinary mosfet

122

00:48:34

Mass hysteresis! But it works. -5, 0, 5 logic.

published 10 years ago

eekee

8 years ago

Ooh goodie! I've been wondering how to do this ever since I got interested in balanced ternary (trinary) computers. By the way, that's not hysteresis, it's typical CMOS gate delay. Modify the transistors to mitigate it: increase width or decrease length. I suppose decreasing length is better as it decreases capacitance and resistance (or should), but I dimly recall being surprised by a lack of difference between the two changes.

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