2017-11-19: Fixed output logic 0 level (twice)
20m CAT-5 driven ECL-style: with a long-tailed pair and emitter-followers. Receiver is 2 more long-tailed pairs putting out 5V logic levels. I'm in love with long-tailed pairs, LOL! They work wonders.
The data source represents ASCII 'u' in 8 bits with 1 start and 1 stop bit at 0-level: (0)01110101(0).
Drops bit(s) at 2Mbps -- I have much more respect for the people who developed 1Gbps Ethernet now! ECL too, my long-tailed pairs don't go fast.
One feature of this design bothers me a little bit: it requires a ground return as well as the twisted pair, which could be inconvenient. I wonder about noise on the ground plane too; it would mostly become common-mode noise, but difference between the actual value of the 2 resistors means some part of the noise may appear differentially across the inputs.
