When input is low, corresponding base emitter junction is forward biased, and base collector junction is reverse biased.
As a result transistor Q2 (collector connected to the 1.6K resistor) is cut off and also transistor Q4 is cut off.
Transistor Q3 (collector connected to the 130Ω resistor) goes to saturation and diode D2 (connected between the emitter and collector of two transistors) starts conducting and output is connected to Vcc and goes to logic high.
Similarly, when input is at logic high, output is at logic low.
Enjoy...😎
