This circuit mimics a 4 bit shift register. Logic train sets data line on or off for serial input across shift register. The astable 555 pulses d flip flops clock inputs to read the data line and increments the counter. Monostable 555 is triggered by the counter when, which resets after it counts 4 pulses from the astable 555. The monostable then pulses the clock clock inputs of the second d flip flop registers. This loads the 4 bits into the secondary register for parallel transmission to a “bus” (green LEDs in this example). The logic train is timed a little out of sync to generate a somewhat random input to the shift register.
