modified 6 years ago

Gated RS Latch

00:43:10

Operation
-------------
Turn the set-bit to 1 followed by 0. Turn the reset-bit to 1 followed by 0. This should bring the circuit to proper operation.
The purple signal represents the clock. 
The green signal represents Q, a stored bit of 1 or 0.
The yellow signal represents ~Q, a reset flag and an indicator that the stored bit is 0.
The top-left logic source represents the set-bit. Toggling this element to the on position (while reset is 0) will store the value 1 in the circuit.
The bottom-left logic source represents the reset-bit. Toggling this element to the on position (while the set-bit is 0) will clear the stored bit and set it back to 0.
Turning both the set-bit and reset-bit on at the same time results in an unstable mode.

published 6 years ago

fatcat2

6 years ago

But this is not an edge triggered latch...

nbbevan

6 years ago

Is there a better name for it?

fatcat2

6 years ago

A flip flop.

fatcat2

6 years ago

Most circuits use them instead of clocked rs latches.

hurz

6 years ago

gated rs latch

nbbevan

6 years ago

Will change the name later today!

hurz

6 years ago

clocked, gated, enabled- rs latch or just d flip flop, and d-ff there are many in its behaviour different ones how the clock for example takes over the data static or on edge, whatever

nbbevan

6 years ago

So like, a clock present in the circuit doesn’t necessarily mean it’s synchronized with it?

fatcat2

6 years ago

Why do you say so?

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