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D Flip-Flop Rising-Edge Trigger

@FalchionGPX
10 years ago
https://everycircuit.com/circuit/6484677471764480
WIP, learning about flip flops. Had to use a OP AMP due to fan out on the last level. Pretty much a gated D-latch, where a timer (The Clock, or Clk) is the gate. I'm using a 555 timer. Top 555 Timer = Gate Bottom 555 Timer = D input. The clock for D (the input) is out of sync (on purpose) with the clock for the gate. Notice what happens to the LEDs.... not quite a discernible rational pattern in their blinks. Block Diogram O' Simplicity Rising Edge, meaning that output Q can only change when clock goes from 0 to 1. When clock goes from 0 to 1, Q = Whatever D happens to be right then. D=input function (on it's own timer) Q=top Clk = 555 timer ______ D- | |-Q (LED output) Clk-| D | |_____|
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