60 Sec digital timer

202

01:50:29

When the input at the left goes high the first two gates generate a brief +Ve  going pulse that sets the SR latch this makes the latches Q  o/p high lighting the LED and allowing the clock generator to increment the counters via the AND gate. When the counters reach 60 (DEC) or 3C(HEX) the output of the and gate to the right goes high resetting the SR latch switching of the LED and resetting the counters via the not Q output of the latch. The cycle is complete and can be retriggered again whenever necessary.

published 9 years ago

basavanagowda

9 years ago

Put 7 segment plz

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