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modified 4 years ago

bit shift register (no clock signal use)

0
3
169
01:03:30
It’s a register designed by some interesting mistakes. The shifting will continue when input signal is HIGH, it will reset after all 4 bits are HIGH and input is LOW.
published 4 years ago
MatthewKessler
4 years ago
ok nice
AlexNU
4 years ago
Ок
AlexNU
4 years ago
Ок

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