CMOS working.. Also U can call NMOS and PMOS Working...

Check your pmos body diode

Ok.. problem solved.. thnks

The present Vgs₍ₜₕ₎ cutoff for this pmos needs to have a gate voltage of about +11.6v here if the gate is to open and close normally. More negative volts beyond zero will not turn the pmos off, contrary to your statement of cutoff. (care.... not  -11.6v on the pmos gate itself, but you will need -11.6v in the back-to-front right gate supply setting to achieve that positive gate value once the switch is moved to the right). An alternative would be to alter the Vgs₍ₜₕ₎ cutoff to make it simulate a Logic Level. Your LED resistors need adjusting, and both of the mosfet settings need alteration to overcome the very wrong Rds₍ₒₙ₎ which is making the mosfets use lots of wasted heat power. I think that sticking to using the pmos the other normal way round is advisable, with the source to a non-earthed positive.

http://everycircuit.com/circuit/6676866922708992

There is one more problem was there in biasing.. i used same Vds biasing for NMOS and PMOS.. i have to reverse that bt did that mistake...

I think nw the circuit is complete... What is ur opinion?

Regarding the left nmos section...it looks basically fine...take a look here and see how the nmos is only dropping 1mV across itself, with a nice current of 20mA. That means the Rds₍ₒₙ₎ is at 0.05 ohms which is normal (so no untoward power/heat loss here)... http://everycircuit.com/circuit/5000262282641408 As for the right pmos section I think that I have said enough.

Ok thanks... I vl make one more time check everything...