3-Bit Asynchronous Count Down

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05:02:25

Asynchronous 'ripple' counter. Counts down from 7 to 0 then repeats. 
(111-110-101-100-011-101-001-000...repeat) 

Controlled via logic source connected to the CLK input of the upper D-type latch.
 
Note: The clock input of the second flip-flop (middle) is skewed by the clock-to-Q propagation delay of the first flip-flop (top). The same happens between the second and third flip-flop (bottom).
This cumulative effect allows the sequence to work but forms a ripple error as seen in the 7-segment display with temporary unintended values. 
This is a know issue with ripple counters; not a mistake in the circuit :-)

published 7 years ago

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